1. Field of the Invention
The present invention relates to a semiconductor device that includes a cell region having a semiconductor chip and an outer peripheral region provided around the cell region. Also, the present invention relates to a method for manufacturing the semiconductor device.
2. Description of Related Art
Conventionally, for example, JP-A-2002-184985 corresponding to U.S. Pat. No. 6,982,459 has described a semiconductor device having a peripheral region (for high voltage use) provided at an outer peripheral region of a superjunction element. Specifically, JP-A-2002-184985 describes the semiconductor device, which has a silicon substrate having a superjunction structure portion. The superjunction structure portion has P type silicon single crystal regions and N type silicon single crystal regions alternately arranged along a surface of the silicon substrate. Also, the semiconductor device further has a cell region and an outer peripheral region that are provided on the silicon substrate. Multiple longitudinal semiconductor chips are formed on the cell region, and the outer peripheral region is provided around the cell region.
In the outer peripheral region of the above semiconductor device, an electric field is remarkably increased on a vicinity of a field plate end portion of the outer peripheral region. As a result, breakdown voltage may degrade. Thus, another superjunction structure other than the superjunction structure of the cell region is formed on the outer peripheral region to reduce the electric field on the outer peripheral region such that the degradation of the breakdown voltage at the outer peripheral region can be avoided.
However, in the above technique, different superjunction structures have to be formed on the silicon substrates of the cell region and the outer peripheral region. Thus, a superjunction structure in accordance with a shape and a size of each semiconductor chip has to be formed for the cell region and the outer peripheral region. As a result, a common substrate that can be used without consideration of the shape and size of the semiconductor chip has not been prepared. Thus, flexibility in usage of the substrate having the superjunction structure has not been fully achieved, and a substrate dedicated to each semiconductor chip has been used inevitably.
Thus, a common pn column structure may be used or shared by the cell region and the outer peripheral structure portion. FIG. 8 shows a cross section of a silicon substrate having a common superjunction structure shared by the cell region and the outer peripheral region. Thus, a silicon substrate 30 is provided with a superjunction structure 31, and a cell region 32 and an outer peripheral region 33 are provided to the substrate 30.
A field plate 34 is formed on the cell region 32 side of the outer peripheral region 33 of the substrate 30 as an electrode portion, and an insulator film 35 is formed on a front face of the outer peripheral region 33. Also, a drain electrode 36 is formed on a back face of the substrate 30. In a semiconductor device having the above structure, for example, in a case of n-channel MOSFET, a positive voltage is applied to a drain 36 relative to a source electrode, a depletion layer emerges as shown by a dashed line in FIG. 8.
In the above semiconductor device, inventors performed simulation of an electric field distribution. FIG. 9 shows a result of the simulation. When a voltage (potential) is distributed at high voltage in a direction from the cell region 32 to the outer peripheral region 33, as shown in FIG. 9, an electric field is high mostly on an end portion of the field plate 34 in the substrate 30. The above distribution is caused by the superjunction structure 31 that is shared by the cell region 32 and the outer peripheral region 33.
As above, when the superjunction structure 31, which is common in the substrate 30, is formed, breakdown voltage may not be sufficiently achieved in the outer peripheral region 33, and thereby breakdown voltage by a semiconductor device degrades.